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Ethernet (ETH): media access control (MAC) with DMA controller
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RDES3: Receive descriptor Word3
RDES3 contains the address pointer either to the second data buffer in the descriptor
or to the next descriptor, or it contains time stamp data.
31 30 29 28 27 26 25
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Bits 31:0 RBAP2 / RTSH: Receive buffer 2 address pointer (next descriptor address) / Receive frame
time stamp high
These bits take on two different functions: the application uses them to indicate to the DMA the
location of where to store the data in memory, and then after transferring all the data the DMA
may use these bits to pass back time stamp data.
RBAP1: When the software makes this descriptor available to the DMA (at the moment that the
OWN bit is set to 1 in RDES0), these bits indicate the physical address of buffer 2 when a
descriptor ring structure is used. If the second address chained (RDES1 [24]) bit is set, this address
contains the pointer to the physical memory where the next descriptor is present. If RDES1 [24] is
set, the buffer (next descriptor) address pointer must be bus width-aligned (RDES3[3, 2, or 1:0]
= 0, corresponding to a bus width of 128, 64 or 32. LSBs are ignored internally.) However, when
RDES1 [24] is reset, there are no limitations on the RDES3 value, except for the following condition:
the DMA uses the configured value for its buffer address generation when the RDES3 value is used to
store the start of frame. The DMA ignores RDES3[3, 2, or 1:0] (corresponding to a bus width of 128,
64 or 32) if the address pointer is to a buffer where the middle or last part of the frame is stored.
RTSH: Before it clears the OWN bt in RDES0, the DMA updates this field with the 32 most
significant bits of the time stamp captured for the corresponding receive frame (overwriting the
value for RBAP2). This field has the time stamp only if time stamping is activated and if the Last
segment control bit (LS) in the descriptor is set.
29.6.9
DMA interrupts
Interrupts can be generated as a result of various events. The ETH_DMASR register
contains all the bits that might cause an interrupt. The ETH_DMAIER register contains an
enable bit for each of the events that can cause an interrupt.
There are two groups of interrupts, Normal and Abnormal, as described in the
ETH_DMASR register. Interrupts are cleared by writing a 1 to the corresponding bit position.
When all the enabled interrupts within a group are cleared, the corresponding summary bit
is cleared. If the MAC core is the cause for assertion of the interrupt, then any of the TSTS
or PMTS bits in the ETH_DMASR register is set high.
Interrupts are not queued and if the interrupt event occurs before the driver has responded
to it, no additional interrupts are generated. For example, the Receive Interrupt bit
(ETH_DMASR register [6]) indicates that one or more frames were transferred to the
STM32F107xx buffer. The driver must scan all descriptors, from the last recorded position to
the first one owned by the DMA.
An interrupt is generated only once for simultaneous, multiple events. The driver must scan
the ETH_DMASR register for the cause of the interrupt. The interrupt is not generated again
unless a new interrupting event occurs, after the driver has cleared the appropriate bit in the
ETH_DMASR register. For example, the controller generates a Receive interrupt
(ETH_DMASR register[6]) and the driver begins reading the ETH_DMASR register. Next,
receive buffer unavailable (ETH_DMASR register[7]) occurs. The driver clears the Receive
1000/1096
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Doc ID 13902 Rev 12
RBP2 / RTSH
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RM0008
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