Ethernet Register Maps; Table 214. Ethernet Register Map And Reset Values - ST STM32F101xx Reference Manual

Ethernet (ETH): media access control (MAC) with DMA controller
29.8.5

Ethernet register maps

Table 214

Table 214. Ethernet register map and reset values

Offset Register
ETH_MACCR
0x00
Reset value
ETH_MACFF
RA
R
0x04
Reset value 0
ETH_MACHT
HR
0x08
Reset value 0 0
ETH_MACHT
LR
0x0C
Reset value 0 0
ETH_MACMII
AR
0x10
Reset value
ETH_MACMII
DR
0x14
Reset value
ETH_MACFC
R
0x18
Reset value 0 0
ETH_MACVL
ANTR
0x1C
Reset value
ETH_MACRW
UFFR
0x28
Reset value
ETH_MACPM
TCSR
0x2C
Reset value 0
ETH_MACSR
0x38
Reset value
ETH_MACIM
R
0x3C
Reset value
ETH_MACA0
HR
0x40
Reset value 1 0
ETH_MACA0
0x44 LR
Reset value 1 1
ETH_MACA1
AE SA
HR
0x48
Reset value 0 0
ETH_MACA1
LR
0x4C
Reset value 1 1
ETH_MACA2
AE SA
HR
0x50
Reset value 0 0
ETH_MACA2
LR
0x54
Reset value 1 1
1042/1096
gives the ETH register map and reset values.
Reserved
0 0
Reserved
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Reserved
Reserved
PT
0 0 0 0 0 0 0 0
Reserved
Frame filter reg0\Frame filter reg1\Frame filter reg2\Frame filter reg3\Frame filter reg4\...\Frame filter reg7
Not applicable
Not applicable
Reserved
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
MBC[6:0]
0 0 0 0 0 0
1 1 1 1 1 1 1 1
MBC
0 0 0 0 0 0
1 1 1 1 1 1 1 1
Doc ID 13902 Rev 12
IFG
0 0 0 0 0
HTH[31:0]
0 0 0 0 0 0 0 0
HTL[31:0]
0 0 0 0 0 0 0 0
PA
0 0
0 0
0 0 0 0 0 0
0 0 0
0
Reserved
Reserved
Reserved
0 0 0 0 0 0 1 1
MACA0L
1 1 1 1 1 1 1 1
Reserved
1 1
MACA1L
1 1 1 1 1 1 1 1
Reserved
1 1
MACA2L
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
MR
0 0 0 0 0 0 0 0
MD
0 0 0 0 0 0 0 0
Reserved
0
VLANTI
0 0 0 0 0 0 0 0
0 0
0 0
Reserved
0
MACA0H
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
MACA1H
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
MACA2H
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
RM0008
0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
M M
CR
W B
0 0 0 0 0
0 0 0 0 0 0
PLT
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0
Reserved
0 0 0
Reserved
0
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1