Debug Mcu Configuration Register - ST STM32F101xx Reference Manual

RM0008
2
For the I
31.16.3

Debug MCU configuration register

This register allows the configuration of the MCU under DEBUG. This concerns:
●
Low-power mode support
●
Timer and watchdog counter support
●
bxCAN communication support
●
Trace pin assignment
This DBGMCU_CR is mapped on the External PPB bus at address 0xE0042004
It is asynchronously reset by the PORESET (and not the system reset). It can be written by
the debugger under system reset.
If the debugger host does not support these features, it is still possible for the user software
to write to these registers.
DBGMCU_CR
Address: 0xE004 2004
Only 32-bit access supported
POR Reset: 0x0000 0000 (not reset by system reset)
31 30 29
DBG_
DBG_
TIM11_ TIM10_
Res.
STOP
STOP
rw rw
15 14 13
DBG_I2C1 DBG_ DBG_
_SMBUS_ CAN1_ TIM4_
TIMEOUT STOP STOP
rw rw rw
Bit 31 Reserved, must be kept cleared.
Bits 30:25 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=9..14)
Bits 24:22
Bit 21 DBG_CAN2_STOP: Debug CAN2 stopped when core is halted
Bits 20:17 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=8..5)
C, the user can choose to block the SMBUS timeout during a breakpoint.
28 27 26 25
DBG_ DBG_
DBG_ DBG_
TIM9_ TIM14_ TIM13_ TIM12_
STOP STOP
STOP STOP
rw rw rw rw
12 11 10 9
DBG_ DBG_ DBG_ DBG_
TIM3_ TIM2_ TIM1_ WWDG_
STOP STOP STOP STOP
rw rw rw rw
0: The clock of the involved timer counter is fed even if the core is halted, and the outputs
behave normally.
1: The clock of the involved timer counter is stopped when the core is halted, and the outputs
are disabled (as if there were an emergency stop in response to a break event).
Reserved, must be kept cleared.
0: Same behavior as in normal mode
1: CAN2 receive registers are frozen
0: The clock of the involved timer counter is fed even if the core is halted, and the outputs
behave normally.
1: The clock of the involved timer counter is stopped when the core is halted, and the outputs
are disabled (as if there were an emergency stop in response to a break event).
Doc ID 13902 Rev 12
24 23 22 21
DGB_C
AN2_ST
Reserved
OP
rw
8 7 6 5
DBG_ TRACE_
TRACE_
IWDG MODE
IOEN
STOP [1:0]
rw rw rw rw
Debug support (DBG)
20 19 18 17
DBG_ DBG_ DBG_ DBG_
TIM7_ TIM6_ TIM5_ TIM8_
STOP STOP STOP STOP
rw rw rw
4 3 2
DBG_
DBG_
STAND
STOP
Reserved
BY
rw
16
DBG_I2C2
_SMBUS_
TIMEOUT
rw rw
1 0
DBG_
SLEEP
rw rw
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