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RM0008
Bit 6 FUGF: Forward undersized good frames
When this bit is set, the Rx FIFO forwards undersized frames (frames with no error and length
less than 64 bytes) including pad-bytes and CRC).
When this bit is cleared, the Rx FIFO drops all frames of less than 64 bytes, unless such a
frame has already been transferred due to lower value of receive threshold (e.g., RTC = 01).
Bit 5 Reserved
Bits 4:3 RTC: Receive threshold control
These two bits control the threshold level of the Receive FIFO. Transfer (request) to DMA
starts when the frame size within the Receive FIFO is larger than the threshold. In addition, full
frames with a length less than the threshold are transferred automatically.
Note: Note that value of 11 is not applicable if the configured Receive FIFO size is 128 bytes.
Note: These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is
Bit 2 OSF: Operate on second frame
When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even
before status for first frame is obtained.
Bit 1 SR: Start/stop receive
When this bit is set, the receive process is placed in the Running state. The DMA attempts to
acquire the descriptor from the receive list and processes incoming frames. Descriptor
acquisition is attempted from the current position in the list, which is the address set by the
DMA ETH_DMARDLAR register or the position retained when the receive process was
previously stopped. If no descriptor is owned by the DMA, reception is suspended and the
receive buffer unavailable bit (ETH_DMASR [7]) is set. The Start Receive command is effective
only when reception has stopped. If the command was issued before setting the DMA
ETH_DMARDLAR register, the DMA behavior is unpredictable.
When this bit is cleared, RxDMA operation is stopped after the transfer of the current frame.
The next descriptor position in the receive list is saved and becomes the current position when
the receive process is restarted. The Stop Receive command is effective only when the
Receive process is in either the Running (waiting for receive packet) or the Suspended state.
Bit 0 Reserved
Ethernet (ETH): media access control (MAC) with DMA controller
set to 1.
00: 64
01: 32
10: 96
11: 128
Doc ID 13902 Rev 12
1037/1096
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