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Ethernet (ETH): media access control (MAC) with DMA controller
transmission has stopped. Once transmission has stopped, the ETH_DMATDLAR register
can be written before the transmission Start command is given.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 STL: Start of transmit list
This field contains the base address of the first descriptor in the transmit descriptor list. The
LSB bits [1/2/3:0] for 32/64/128-bit bus width) are internally ignored and taken as all-zero by
the DMA. Hence these LSB bits are read-only.
Ethernet DMA status register (ETH_DMASR)
Address offset: 0x1014
Reset value: 0x0000 0000
The Status register contains all the status bits that the DMA reports to the application. The
ETH_DMASR register is usually read by the software driver during an interrupt service
routine or polling. Most of the fields in this register cause the host to be interrupted. The
ETH_DMASR register bits are not cleared when read. Writing 1 to (unreserved) bits in
ETH_DMASR register[16:0] clears them and writing 0 has no effect. Each field (bits [16:0])
can be masked by masking the appropriate bit in the ETH_DMAIER register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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Bits 31:30 Reserved
Bit 29 TSTS: Time stamp trigger status
This bit indicates an interrupt event in the MAC core's Time stamp generator block. The
software must read the MAC core's status register, clearing its source (bit 9), to reset this bit to
0. When this bit is high an interrupt is generated if enabled.
Bit 28 PMTS: PMT status
This bit indicates an event in the MAC core's PMT. The software must read the corresponding
registers in the MAC core to get the exact cause of interrupt and clear its source to reset this bit
to 0. The interrupt is generated when this bit is high if enabled.
Bit 27 MMCS: MMC status
This bit reflects an event in the MMC of the MAC core. The software must read the
corresponding registers in the MAC core to get the exact cause of interrupt and clear the
source of interrupt to make this bit as 0. The interrupt is generated when this bit is high if
enabled.
Bit 26 Reserved
1032/1096
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Doc ID 13902 Rev 12
STL
rc-
rc-
rc-
rc-
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w1
w1
w1
w1
9
8
7
6
5
4
9
8
7
6
5
4
rc-
rc-
rc-
rc-
rc-
rc-
rc-
w1
w1
w1
w1
w1
w1
w1
RM0008
3
2
1
0
3
2
1
0
rc-
rc-
rc-
rc-
w1
w1
w1
w1
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