Table 213. Receive Descriptor 0 - ST STM32F101xx Reference Manual

RM0008
Bit 3 RE: Receive error
When set, this bit indicates that the RX_ERR signal is asserted while RX_DV is asserted during
frame reception.
Bit 2 DE: Dribble bit error
When set, this bit indicates that the received frame has a non-integer multiple of bytes (odd
nibbles). This bit is valid only in MII mode.
Bit 1 CE: CRC error
When set, this bit indicates that a cyclic redundancy check (CRC) error occurred on the
received frame. This field is valid only when the last descriptor (RDES0[8]) is set.
Bit 0 PCE: Payload checksum error
When set, it indicates that the TCP, UDP or ICMP checksum the core calculated does not
match the received encapsulated TCP, UDP or ICMP segment's Checksum field. This bit is also
set when the received number of payload bytes does not match the value indicated in the
Length field of the encapsulated IPv4 or IPv6 datagram in the received Ethernet frame.
Bits 5, 7, and 0 reflect the conditions discussed in

Table 213. Receive descriptor 0

Bit 5:
frame
type
0
1
1
1
1
0
0
0
Ethernet (ETH): media access control (MAC) with DMA controller
Bit 7: IPC Bit 0: payload
checksum checksum
error error
0 0
0 0
0 1
1 0
1 1
0 1
1 1
1 0
Doc ID 13902 Rev 12
Table 213.
Frame status
IEEE 802.3 Type frame (Length field value is less than
0x0600.)
IPv4/IPv6 Type frame, no checksum error detected
IPv4/IPv6 Type frame with a payload checksum error (as described
for PCE) detected
IPv4/IPv6 Type frame with an IP header checksum error (as
described for IPC CE) detected
IPv4/IPv6 Type frame with both IP header and payload checksum
errors detected
IPv4/IPv6 Type frame with no IP header checksum error and the
payload check bypassed, due to an unsupported payload
A Type frame that is neither IPv4 or IPv6 (the checksum offload
engine bypasses checksum completely.)
Reserved
997/1096