Clearing The Ocxref Signal On An External Event; Figure 90. Clearing Timx Ocxref - ST STM32F101xx Reference Manual

Advanced arm-based 32-bit mcus

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Clearing the OCxREF signal on an external event

The OCxREF signal for a given channel can be driven Low by applying a High level to the

ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to '1'). The

OCxREF signal remains Low until the next update event, UEV, occurs.

This function can only be used in output compare and PWM modes, and does not work in

forced mode.

For example, the OCxREF signal) can be connected to the output of a comparator to be

used for current handling. In this case, the ETR must be configured as follow:

The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR

The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to

The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be

configured according to the user needs.

for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in

counter (CNT)

shows the behavior of the OCxREF signal when the ETRF Input becomes High,

Doc ID 13902 Rev 12

Advanced-control timers (TIM1&TIM8)

becomes high