Figure 197. Muxed Read Accesses; Figure 198. Muxed Write Accesses - ST STM32F101xx Reference Manual

RM0008
Mode muxed - asynchronous access muxed NOR Flash

Figure 197. Muxed read accesses

1. The bus turnaround delay (BUSTURN + 1) and the delay between side-by-side transactions overlap, so
BUSTURN ≤5 has not impact.

Figure 198. Muxed write accesses

The difference with mode D is the drive of the lower address byte(s) on the databus.
A[25:16]
NADV
NEx
NOE
NWE
High
AD[15:0]
Lower address
(ADDSET +1)
HCLK cycles
A[25:16]
NADV
NEx
NOE
NWE
AD[15:0]
Doc ID 13902 Rev 12
Flexible static memory controller (FSMC)
Memory transaction
1HCLK cycle
(DATAST + 1)
HCLK cycles
(ADDHLD + 1)
HCLK cycles
Data sampled
Memory transaction
Lower address
(ADDSET +1) ADDHLD
HCLK cycles
HCLK cycles
data driven
by memory
(1)
2 HCLK (BUSTURN + 1)
cycles HCLK cycles
Data strobe
1HCLK
data driven by FSMC
(DATAST + 2)
HCLK cycles
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