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Ethernet (ETH): media access control (MAC) with DMA controller
Bits 4:2 CR: Clock range
The CR clock range selection determines the HCLK frequency and is used to decide the
frequency of the MDC clock:
Bit 1 MW: MII write
When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If
this bit is not set, this will be a Read operation, placing the data in the MII Data register.
Bit 0 MB: MII busy
This bit should read a logic 0 before writing to ETH_MACMIIAR and ETH_MACMIIDR. This bit
must also be reset to 0 during a Write to ETH_MACMIIAR. During a PHY register access, this
bit is set to 0b1 by the application to indicate that a read or write access is in progress.
ETH_MACMIIDR (MII Data) should be kept valid until this bit is cleared by the MAC during a
PHY Write operation. The ETH_MACMIIDR is invalid until this bit is cleared by the MAC during
a PHY Read operation. The ETH_MACMIIAR (MII Address) should not be written to until this bit
is cleared.
Ethernet MAC MII data register (ETH_MACMIIDR)
Address offset: 0x0014
Reset value: 0x0000 0000
The MAC MII Data register stores write data to be written to the PHY register located at the
address specified in ETH_MACMIIAR. ETH_MACMIIDR also stores read data from the PHY
register located at the address specified by ETH_MACMIIAR.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved
Bits 15:0 MD: MII data
This contains the 16-bit data value read from the PHY after a Management Read operation, or
the 16-bit data value to be written to the PHY before a Management Write operation.
Ethernet MAC flow control register (ETH_MACFCR)
Address offset: 0x0018
Reset value: 0x0000 0000
The Flow control register controls the generation and reception of the control (Pause
Command) frames by the MAC. A write to a register with the Busy bit set to '1' causes the
MAC to generate a pause control frame. The fields of the control frame are selected as
specified in the 802.3x specification, and the Pause Time value from this register is used in
the Pause Time field of the control frame. The Busy bit remains set until the control frame is
1008/1096
Selection
HCLK
000
60-72 MHz
001
Reserved
010
20-35 MHz
011
35-60 MHz
100, 101, 110, 111 Reserved
Reserved
Doc ID 13902 Rev 12
MDC Clock
HCLK/42
-
HCLK/16
HCLK/26
-
9
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
RM0008
8
7
6
5
4
3
2
MD
1
0
rw
rw
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