ST STM32F101xx Reference Manual page 1023

RM0008
Ethernet MMC transmitted good frames counter register (ETH_MMCTGFCR)
Address offset: 0x0168
Reset value: 0x0000 0000
This register contains the number of good frames transmitted.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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Bits 31:0 TGFC: Transmitted good frames counter
Ethernet MMC received frames with CRC error counter register
(ETH_MMCRFCECR)
Address offset: 0x0194
Reset value: 0x0000 0000
This register contains the number of frames received with CRC error.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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Bits 31:0 RFCEC: Received frames CRC error counter
Received frames with CRC error counter
Ethernet MMC received frames with alignment error counter register
(ETH_MMCRFAECR)
Address offset: 0x0198
Reset value: 0x0000 0000
This register contains the number of frames received with alignment (dribble) error.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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Bits 31:0 RFAEC: Received frames alignment error counter
Received frames with alignment error counter
Ethernet (ETH): media access control (MAC) with DMA controller
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Doc ID 13902 Rev 12
TGFC
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RFCEC
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RFAEC
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9 8 7 6 5 4
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9 8 7 6 5 4
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9 8 7 6 5 4
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3 2 1 0
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3 2 1 0
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3 2 1 0
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