Mpu Mismatch; Updating An Mpu Region; Table 41. Ap Encoding - ST STM32H7 Series Programming Manual

Core peripherals
Table 41
unprivileged software.
AP[2:0]
000
001
010
011
100
101
110
111
4.2.2

MPU mismatch

When an access violates the MPU permissions, the processor generates a memory
management fault, see
indicates the cause of the fault. See
register (MMFAR) on page 242
4.2.3

Updating an MPU region

To update the attributes for an MPU region, update the MPU_RNR, MPU_RBAR and
MPU_RASR registers. You can program each register separately, or use a multiple-word
write to program all of these registers. You can use the MPU_RBAR and MPU_RASR
aliases to program up to four regions simultaneously using an STM instruction.
Updating an MPU region using separate words
Simple code to configure one region:
LDR R0,=MPU_RNR
STR R1, [R0, #0x0]
STR R4, [R0, #0x4]
STRH R2, [R0, #0x8]
STRH R3, [R0, #0xA]
Disable a region before writing new region settings to the MPU if you have previously
enabled the region being changed. For example:
196/262
shows the AP encodings that define the access permissions for privileged and
Privileged
permissions
No access
RW
RW
RW
Unpredictable
RO
RO
RO
Section 2.1.4: Exceptions and interrupts on page
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
; 0xE000ED98, MPU region number register
; Region Number
; Region Base Address
; Region Size and Enable
; Region Attribute
; R1 = region number
; R2 = size/enable

Table 41. AP encoding

Unprivileged
permissions
No access All accesses generate a permission fault
No access Access from privileged software only
Writes by unprivileged software generate
RO
a permission fault
RW Full access
Unpredictable Reserved
No access Reads by privileged software only
Read only, by privileged or unprivileged
RO
software
Read only, by privileged or unprivileged
RO
software
Section 4.4.15: Memory management fault address
for more information.
PM0214 Rev 9
PM0214
Description
26. The MMFSR