Mpu Region Attribute And Size Register (Mpu_Rasr) - ST STM32H7 Series Programming Manual

Core peripherals
4.2.9

MPU region attribute and size register (MPU_RASR)

Address offset: 0x10
Reset value: 0x0000 0000
Required privilege: Privileged
The MPU_RASR register defines the region size and memory attributes of the MPU region
specified by the MPU_RNR, and enables that region and any subregions.
MPU_RASR is accessible using word or halfword accesses:
•
The most significant halfword holds the region attributes
• The least significant halfword holds the region size and the region and subregion
enable bits.
31 30 29 28
Reserved XN
rw
15 14 13 12
rw rw rw rw
Bits 31:29 Reserved, forced by hardware to 0.
Bit 28 XN: Instruction access disable bit:
Bit 27 Reserved, forced by hardware to 0.
Bits 26:24 AP[2:0]: Access permission
For information about access permission, see
Bits 23:22 Reserved, forced by hardware to 0.
Bits 21:19 TEX[2:0]: memory attribute
For a description of TEX bits encoding refer to
Bit 18 S: Shareable memory attribute
For a description of S bits encoding refer to
Bit 17 C: memory attribute
Bit 16 B: memory attribute
204/262
27 26 25
AP[2:0]
rw rw
11 10 9
SRD[7:0]
rw rw rw
0: Instruction fetches enabled
1: Instruction fetches disabled.
For a description of AP bits encoding refer to
24 23 22
Reserved
rw
8 7 6
Reserved
rw
Section 4: Core peripherals
Table 41 on page
Table 39 on page 195
Table 39 on page 195
PM0214 Rev 9
21 20 19 18
TEX[2:0] S
rw rw rw rw
5 4 3 2
SIZE
rw rw rw rw
196.
PM0214
17 16
C B
rw rw
1 0
rw rw