Address Alignment; Pc-Relative Expressions; Conditional Execution - ST STM32F3 Series Programming Manual

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3.3.5

Address alignment

An aligned access is an operation where a word-aligned address is used for a word, dual
word, or multiple word access, or where a halfword-aligned address is used for a halfword
access. Byte accesses are always aligned.
The Cortex-M4 processor supports unaligned access only for the following instructions:
•
LDR, LDRT
•
LDRH, LDRHT
•
LDRSH, LDRSHT
•
STR, STRT
•
STRH, STRHT
All other load and store instructions generate a usage fault exception if they perform an
unaligned access, and therefore their accesses must be address aligned. For more
information about usage faults see
Unaligned accesses are usually slower than aligned accesses. In addition, some memory
regions might not support unaligned accesses. Therefore, Arm recommends that
programmers to ensure that accesses are aligned. To avoid accidental generation of
unaligned accesses, use the UNALIGN_TRP bit in the configuration and control register to
trap all unaligned accesses, see
3.3.6

PC-relative expressions

A PC-relative expression or label is a symbol that represents the address of an instruction or
literal data. It is represented in the instruction as the PC value plus or minus a numeric
offset. The assembler calculates the required offset from the label and the address of the
current instruction. If the offset is too big, the assembler produces an error.
•
For the B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the
current instruction plus four bytes.
•
For all other instructions that use labels, the value of the PC is the address of the
current instruction plus four bytes, with bit[1] of the result cleared to 0 to make it word-
aligned.
•
Your assembler might permit other syntaxes for PC-relative expressions, such as a
label plus or minus a number, or an expression of the form [PC, #number].
3.3.7

Conditional execution

Most data processing instructions can optionally update the condition flags in the application
program status register (APSR) according to the result of the operation (see
program status register on page
update a subset. If a flag is not updated, the original value is preserved. See the instruction
descriptions for the flags they affect.
You can execute an instruction conditionally, based on the condition flags set in another
instruction:
•
Immediately after the instruction that updated the flags
•
After any number of intervening instructions that have not updated the flags
The STM32 Cortex-M4 instruction set
Fault handling on page
Configuration and control register (CCR) on page
21). Some instructions update all flags, and some only
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