Memory Regions, Types And Attributes; Memory System Ordering Of Memory Accesses; Table 12. Ordering Of Memory Accesses - ST STM32H7 Series Programming Manual

PM0214
2.2.1

Memory regions, types and attributes

The memory map and the programming of the MPU splits the memory map into regions.
Each region has a defined memory type, and some regions have additional memory
attributes. The memory type and attributes determine the behavior of accesses to the
region.
The memory types are:
Normal
Device
Strongly-ordered
The different ordering requirements for Device and Strongly-ordered memory mean that the
memory system can buffer a write to Device memory, but must not buffer a write to Strongly-
ordered memory.
The additional memory attributes include:
Execute Never (XN)
2.2.2

Memory system ordering of memory accesses

For most memory accesses caused by explicit memory access instructions, the memory
system does not guarantee that the order, in which the accesses complete, matches the
program order of the instructions, providing this does not affect the behavior of the
instruction sequence. Normally, if correct program execution depends on two memory
accesses completing in program order, software must insert a memory barrier instruction
between the memory access instructions, see
accesses on page
However, the memory system does guarantee some ordering of accesses to Device and
Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs
before A2 in program order, the ordering of the memory accesses caused by two
instructions is:
Normal access
Device access, non-shareable
Device access, shareable
Strongly ordered access
1. - means that the memory system does not guarantee the ordering of the accesses.
< means that accesses are observed in program order, that is, A1 is always observed before A2.
The processor can re-order transactions for efficiency, or
perform speculative reads.
The processor preserves transaction order relative to other
transactions to Device or Strongly-ordered memory.
The processor preserves transaction order relative to all other
transactions.
Means that the processor prevents instruction accesses. Any
attempt to fetch an instruction from an XN region causes a
memory management fault exception.
31.

Table 12. Ordering of memory accesses

A1
Normal access
PM0214 Rev 9
Section 2.2.4: Software ordering of memory
Device access
Non-shareable
- -
- <
- -
- <
The Cortex-M4 processor
(1)
A2
Strongly
ordered
Shareable
access
-
-
<
<
-
<
<
<
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