Clrex - ST STM32H7 Series Programming Manual

The STM32 Cortex-M4 instruction set
Restrictions
In these instructions:
•
Do not use PC.
•
Do not use SP for Rd and Rt.
•
For STREX, Rd must be different from both Rt and Rn.
•
The value of offset must be a multiple of four in the range 0-1020.
Condition flags
These instructions do not change the flags.
Examples
MOV R1, #0x1
LDREX R0, [LockAddr]
CMP R0, #0
ITT EQ
STREXEQ R0, R1, [LockAddr]
CMPEQ R0, #0
BNE try
3.4.9

CLREX

Clear Exclusive.
Syntax
CLREX{cond}
Where:
'cond' is an optional condition code (see
Operation
Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination
register and fail to perform the store. It is useful in exception handler code to force the failure
of the store exclusive if the exception occurs between a load exclusive instruction and the
matching store exclusive instruction in a synchronization operation.
See Synchronization primitives on page 34
Condition flags
These instructions do not change the flags.
Examples
CLREX
80/262
; initialize the 'lock taken' value try
; load the lock value
; is the lock free?
; IT instruction for STREXEQ and CMPEQ
; try and claim the lock
; did this succeed?
; no – try again
; yes – we have the lock
Conditional execution on page
for more information.
PM0214 Rev 9
PM0214
65)