The Stm32 Cortex-M4 Instruction Set; Instruction Set Summary; Table 21. Cortex-M4 Instructions - ST STM32H7 Series Programming Manual

The STM32 Cortex-M4 instruction set

3 The STM32 Cortex-M4 instruction set
This chapter is the reference material for the Cortex-M4 instruction set description in a User
Guide. The following sections give general information:
Section 3.1: Instruction set summary on page 50
Section 3.2: CMSIS intrinsic functions on page 58
Section 3.3: About the instruction descriptions on page 60
Each of the following sections describes a functional group of Cortex-M4 instructions.
Together they describe all the instructions supported by the Cortex-M4 processor:
Section 3.4: Memory access instructions on page 69
Section 3.5: General data processing instructions on page 81
Section 3.6: Multiply and divide instructions on page 109
Section 3.7: Saturating instructions on page 125
Section 3.8: Packing and unpacking instructions on page 134
Section 3.9: Bitfield instructions on page 138
Section 3.10: Floating-point instructions on page 149
Section 3.11: Miscellaneous instructions on page 180
3.1

Instruction set summary

The processor implements a version of the thumb instruction set.
supported instructions.
In Table
•
Angle brackets, <>, enclose alternative forms of the operand.
• Braces, {}, enclose optional operands.
•
The operands column is not exhaustive.
• Op2 is a flexible second operand that can be either a register or a constant.
•
Most instructions can use an optional condition code suffix.
For more information on the instructions and operands, see the instruction descriptions.
Mnemonic
ADC, ADCS
ADD, ADDS
ADD, ADDW {Rd,} Rn, #imm12
ADR
50/262
21:

Table 21. Cortex-M4 instructions

Operands
{Rd,} Rn, Op2
{Rd,} Rn, Op2
Rd, label
Brief description
Add with carry
Add
Add
Load PC-relative address
PM0214 Rev 9
PM0214
Table 21 lists the
Flags Page
N,Z,C,V 3.5.1 on page 83
N,Z,C,V 3.5.1 on page 83
N,Z,C,V 3.5.1 on page 83
— 3.4.1 on page 70