Memory Access Instructions; Table 25. Memory Access Instructions - ST STM32F3 Series Programming Manual

PM0214
3.4

Memory access instructions

Table 25
Mnemonic
ADR
CLREX
LDM{mode}
LDR{type}
LDR{type}
LDR{type}T
LDR
LDRD
LDREX{type} Load register exclusive
POP
PUSH
STM{mode}
STR{type}
STR{type}
STR{type}T
STREX{type} Store register exclusive
shows the memory access instructions:

Table 25. Memory access instructions

Brief description
Load PC-relative address
Clear exclusive
Load multiple registers
Load register using immediate offset
Load register using register offset
Load register with unprivileged access
Load register using PC-relative address
Load register dual
Pop registers from stack
Push registers onto stack
Store multiple registers
Store register using immediate offset
Store register using register offset
Store register with unprivileged access
The STM32 Cortex-M4 instruction set
ADR on page 70
CLREX on page 80
LDM and STM on page 76
LDR and STR, immediate offset on page 71
LDR and STR, register offset on page 73
LDR and STR, unprivileged on page 74
LDR, PC-relative on page 75
LDR and STR, immediate offset on page 71
LDREX and STREX on page 79
PUSH and POP on page 78
PUSH and POP on page 78
LDM and STM on page 76
LDR and STR, immediate offset on page 71
LDR and STR, register offset on page 73
LDR and STR, unprivileged on page 74
LDREX and STREX on page 79
PM0214 Rev 10
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