Table 6. Ipsr Bit Definitions - ST STM32H7 Series Programming Manual

The Cortex-M4 processor
Interrupt program status register
The IPSR contains the exception type number of the current Interrupt Service Routine
(ISR). See the register summary in
The bit assignment is:
Bits
Bits 31:9
Bits 8:0
1. Depends on product. Refer to reference manual/datasheet of relevant STM32 product for related
information.
Execution program status register
The EPSR contains the Thumb state bit, and the execution state bits for either the:
•
If-Then (IT) instruction
•
Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store
multiple instruction.
See the register summary in
is:
22/262

Table 6. IPSR bit definitions

Reserved
ISR_NUMBER:
This is the number of the current exception:
0: Thread mode
1: Reserved
2: NMI
3: Hard fault
4: Memory management fault
5: Bus fault
6: Usage fault
7: Reserved
....
10: Reserved
11: SVCall
12: Reserved for Debug
13: Reserved
14: PendSV
15: SysTick
(1)
16: IRQ0
....
....
(1)
255: IRQ240
see Exception types on page 37
Table 3 on page 18
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Table 3 on page 18 for its attributes.
Description
for more information.
for the EPSR attributes. The bit assignment
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