PM0214
2
The Cortex-M4 processor
2.1
Programmers model
This section describes the Cortex-M4 programmer's model. In addition to the individual core
register descriptions, it contains information about the processor modes and privilege levels
for software execution and stacks.
2.1.1
Processor mode and privilege levels for software execution
The processor modes are:
Thread mode: Used to execute application software.
Handler mode: Used to handle exceptions.
The privilege levels for software execution are:
Unprivileged: Unprivileged software executes at the unprivileged level and:
Privileged:
2.1.2
Stacks
The processor uses a full descending stack. This means the stack pointer indicates the last
stacked item on the stack memory. When the processor pushes a new item onto the stack, it
decrements the stack pointer and then writes the item to the new memory location. The
processor implements two stacks, the main stack and the process stack, with independent
copies of the stack pointer, see
In Thread mode, the CONTROL register controls whether the processor uses the main
stack or the process stack, see
processor always uses the main stack. The options for processor operations are:
The processor enters Thread mode when it comes out of reset.
The CONTROL register controls whether software execution is
privileged or unprivileged, see
The processor returns to Thread mode when it has finished exception
processing.
Software execution is always privileged.
•
Has limited access to the MSR and MRS instructions, and cannot
use the CPS instruction.
•
Cannot access the system timer, NVIC, or system control block.
•
Might have restricted access to memory or peripherals.
•
Must use the SVC instruction to make a supervisor call to transfer
control to privileged software.
Privileged software executes at the privileged level and can use all the
instructions and has access to all resources.
Can write to the CONTROL register to change the privilege level for
software execution.
Stack pointer on page
CONTROL register on page
PM0214 Rev 9
The Cortex-M4 processor
CONTROL register on page
19.
25. In Handler mode, the
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