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STM32F078VB
ST STM32F078VB Manuals
Manuals and User Guides for ST STM32F078VB. We have
1
ST STM32F078VB manual available for free PDF download: Errata Sheet
ST STM32F078VB Errata Sheet (21 pages)
Brand:
ST
| Category:
Computer Hardware
| Size: 0 MB
Table of Contents
Table of Contents
2
Summary of Device Limitations
4
Description of Device Limitations
6
Usart
6
Start Bit Detected too Soon When Sampling for NACK Signal from
6
The Smartcard
6
Break Request Can Prevent the Transmission Complete Flag (TC)
6
From Being Set
6
Nrts Is Active While RE or UE = 0
6
Receiver Timeout Counter Starting in Case of 2 Stops Bit Configuration
7
USART4 Transmission Does Not Work on PC11
7
Last Byte Written in TDR Might Not be Transmitted if te Is Cleared Just after Writing in TDR
7
Gpio
7
Gpiox Locking Mechanism Not Working Properly for Gpiox_Otyper
7
Register
7
Wrong Data Sampling When Data Set-Up Time (T SU;DAT ) Is Shorter than
8
One I2CCLK Period
8
Spurious Bus Error Detection in Master Mode
8
10-Bit Slave Mode: Wrong Direction Bit Value after Read Header
8
Reception
8
10-Bit Combined with 7-Bit Slave Mode: ADDCODE May Indicate Wrong Slave Address Detection
9
Wakeup Frames May Not Wakeup the MCU Mode When STOP Mode
10
Entry Follows I 2 C Enabling
10
Hd;Sta
10
HSI Startup Time
10
Wrong Behavior in Stop Mode When Wakeup from Stop Mode Is Disabled in I 2 C
11
10-Bit Master Mode: New Transfer Cannot be Launched if First Part of the Address Has Not Been Acknowledged by the Slave
11
Spi
12
BSY Bit May Stay High When SPI Is Disabled
12
BSY Bit May Stay High at the End of a Data Transfer in Slave Mode
12
Wrong CRC Transmitted in Master Mode with Delayed SCK Feedback
13
CRC Error in SPI Slave Mode if Internal NSS Changes before CRC
13
Transfer
13
SPI CRC Corrupted Upon DMA Transaction Completion by Another
13
Peripheral
13
In I 2 S Slave Mode: WS Level Must be Set by the External Master When
14
Enabling the I2S
14
Usb
14
The USB BCD Functionality Limited below -20°C
14
DCD (Data Contact Detect) Function Not Compliant
14
Rtc
15
Spurious Tamper Detection When Disabling the Tamper Channel
15
A Tamper Event Preceding the Tamper Detect Enable Not Detected
15
RTC Calendar Registers Are Not Locked Properly
15
Adc
16
Overrun Flag Not Set if EOC Reset Coincides with New Conversion End
16
ADEN Bit Cannot be Set Immediately after the ADC Calibration
16
Comp
16
Long VREFINT Scaler Startup Time after Power on
16
Cec
17
Transmission Blocked When Transmitted Start Bit Is Corrupted
17
Tsc
17
Inhibited Acquisition in Short Transfer Phase Configuration
17
Iwdg
18
RVU, PVU and WVU Flags Are Not Reset in STOP Mode
18
RVU, PVU and WVU Flags Are Not Reset with Low-Frequency APB
18
Revision History
19
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