Asr, Lsl, Lsr, Ror, And Rrx - ST STM32H7 Series Programming Manual

The STM32 Cortex-M4 instruction set
Condition flags
If S is specified, these instructions:
•
Update the N and Z flags according to the result.
•
Can update the C flag during the calculation of operand2, see
on page
•
Do not affect the V flag.
Examples
AND R9, R2,#0xFF00
ORREQ R2, R0, R5
ANDS R9, R8, #0x19
EORS R7, R11, #0x18181818
BIC R0, R1, #0xab
ORN R7, R11, R14, ROR #4
ORNS R7, R11, R14, ASR #32
3.5.3

ASR, LSL, LSR, ROR, and RRX

Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right
with Extend.
Syntax
op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
Where:
•
'op' is one of the following:
ASR: Arithmetic Shift Right
LSL: Logical Shift Left
LSR: Logical Shift Right
ROR: Rotate Right
• 'S' is an optional suffix. If S is specified, the condition code flags are updated on the
result of the operation, see
•
'Rd' is the destination register.
•
'Rm' is the register holding the value to be shifted.
•
'Rs' is the register holding the shift length to apply to the value Rm. Only the least
significant byte is used and can be in the range 0 to 255.
•
'n' is the shift length. The range of shift lengths depends on the instruction as follows:
ASR: Shift length from 1 to 32
LSL: Shift length from 0 to 31
LSR: Shift length from 1 to 32
ROR: Shift length from 1 to 31
Note: MOVS Rd, Rm is the preferred syntax for LSLS Rd, Rm, #0.
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60.
Conditional execution on page
PM0214 Rev 9
PM0214
Flexible second operand
65.