Tbb And Tbh - ST STM32H7 Series Programming Manual

PM0214
3.9.8

TBB and TBH

Table Branch Byte and Table Branch Halfword.
Syntax
TBB [Rn, Rm]
TBH [Rn, Rm, LSL #1]
Where:
•
'Rn' is the register containing the address of the table of branch lengths.
If Rn is PC, then the address of the table is the address of the byte immediately
following the TBB or TBH instruction.
•
'Rm' is the index register. This contains an index into the table. For halfword tables,
LSL #1 doubles the value in Rm to form the right offset into the table.
Operation
These instructions cause a PC-relative forward branch using a table of single byte offsets for
TBB, or halfword offsets for TBH. Rn provides a pointer to the table, and Rm supplies an
index into the table. For TBB the branch offset is twice the unsigned value of the byte
returned from the table. and for TBH the branch offset is twice the unsigned value of the
halfword returned from the table. The branch occurs to the address at that offset from the
address of the byte immediately after the TBB or TBH instruction.
Restrictions
The restrictions are:
•
Rn must not be SP
• Rm must not be SP and must not be PC
•
When any of these instructions is used inside an IT block, it must be the last instruction
of the IT block.
Condition flags
These instructions do not change the flags.
Examples
ADR.W
TBB [R0, R1] ; R1 is the index, R0 is the base address of the branch table
Case1
Case2
Case3
BranchTable_Byte
DCB
DCB
DCB
TBH
R0, BranchTable_Byte
; an instruction sequence follows
; an instruction sequence follows
; an instruction sequence follows
0
((Case2-Case1)/2)
((Case3-Case1)/2)
[PC, R1, LSL #1]
The STM32 Cortex-M4 instruction set
; Case1 offset calculation
; Case2 offset calculation
; Case3 offset calculation
; R1 is the index, PC is used as base of the
; branch table
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