Table 8. Primask Register Bit Definitions; Table 9. Faultmask Register Bit Definitions; Figure 5. Primask Bit Assignment; Figure 6. Faultmask Bit Assignment - ST STM32F3 Series Programming Manual

The Cortex-M4 processor
To access the exception mask registers use the MSR and MRS instructions, or the CPS
instruction to change the value of PRIMASK or FAULTMASK. See
on page
Priority mask register
The PRIMASK register prevents the activation of all exceptions with configurable priority.
See the register summary in
assignment.
31
Bits
Bits 31:1
Bit 0
Fault mask register
The FAULTMASK register prevents activation of all exceptions except for Non-Maskable
Interrupt (NMI). See the register summary in
shows the bit assignment.
31
Bits
Bits 31:1
Bit 0
The processor clears the FAULTMASK bit to 0 on exit from any exception handler except
the NMI handler.
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187, and CPS on page 182
Table 3 on page 18

Figure 5. PRIMASK bit assignment

Table 8. PRIMASK register bit definitions

Reserved
PRIMASK:
0: No effect
1: Prevents the activation of all exceptions with configurable priority.

Figure 6. FAULTMASK bit assignment

Table 9. FAULTMASK register bit definitions

Reserved
FAULTMASK:
0: No effect
1: Prevents the activation of all exceptions except for NMI.
for more information.
for its attributes.
Reserved
Description
Table 3 on page 18
Reserved
Function
PM0214 Rev 10
PM0214
MRS on page 186, MSR
Figure 5 shows the bit
1 0
PRIMASK
for its attributes. Figure 6
1 0
FAULTMASK