Sign In
Upload
Manuals
Brands
ST Manuals
Computer Hardware
STM32F038C6T6
ST STM32F038C6T6 Manuals
Manuals and User Guides for ST STM32F038C6T6. We have
1
ST STM32F038C6T6 manual available for free PDF download: Errata Sheet
ST STM32F038C6T6 Errata Sheet (21 pages)
Brand:
ST
| Category:
Computer Hardware
| Size: 0 MB
Table of Contents
Table of Contents
2
Summary of Device Limitations
4
Description of Device Limitations
6
Usart
6
Start Bit Detected too Soon When Sampling for NACK Signal from
6
The Smartcard
6
Break Request Can Prevent the Transmission Complete Flag (TC)
6
From Being Set
6
Nrts Is Active While RE or UE = 0
6
Consistency Not Checked in Mode 1 of Automatic Baud Rate
7
Detection
7
Framing Error (FE) Flag Low Upon Automatic Baud Rate Detection Error
7
Communication Parameters Reprogramming after ATR in Smartcard Mode When SCLK Is Used to Clock the Card
7
Last Byte Written in TDR Might Not be Transmitted if te Is Cleared Just after Writing in TDR
7
Gpio
8
Extra Consumption on Gpios PB0
8
Gpiox Locking Mechanism Not Working Properly for Gpiox_Otyper
8
Register
8
Wrong Data Sampling When Data Set-Up Time (T SU;DAT ) Is Shorter than
8
One I2CCLK Period
8
Spurious Bus Error Detection in Master Mode
9
10-Bit Slave Mode: Wrong Direction Bit Value after Read Header
9
Reception
9
10-Bit Combined with 7-Bit Slave Mode: ADDCODE May Indicate Wrong Slave Address Detection
10
Wakeup Frames May Not Wakeup the MCU Mode When STOP Mode Entry Follows I 2 C Enabling
10
Hd;Sta
11
HSI Startup Time
11
Wrong Behavior in Stop Mode When Wakeup from Stop Mode Is
11
10-Bit Master Mode: New Transfer Cannot be Launched if First Part of the Address Has Not Been Acknowledged by the Slave
12
Spi
12
BSY Bit May Stay High When SPI Is Disabled
12
BSY Bit May Stay High at the End of a Data Transfer in Slave Mode
13
Wrong CRC Transmitted in Master Mode with Delayed SCK Feedback
13
CRC Error in SPI Slave Mode if Internal NSS Changes before CRC
14
Transfer
14
SPI CRC Corrupted Upon DMA Transaction Completion by Another
14
Peripheral
14
Corrupted Last Bit of Data And/Or CRC, Received in Master Mode with Delayed SCK Feedback
14
Packing Mode Limitation at Reception
15
In I S Slave Mode: WS Level Must be Set by the External Master When Enabling the I2S
16
Rtc
16
Spurious Tamper Detection When Disabling the Tamper Channel
16
A Tamper Event Preceding the Tamper Detect Enable Not Detected
16
RTC Calendar Registers Are Not Locked Properly
17
Adc
17
Overrun Flag Not Set if EOC Reset Coincides with New Conversion End
17
ADEN Bit Cannot be Set Immediately after the ADC Calibration
17
Iwdg
18
RVU, PVU and WVU Flags Are Not Reset in STOP Mode
18
RVU, PVU and WVU Flags Are Not Reset with Low-Frequency APB
18
Revision History
19
Advertisement
Advertisement
Related Products
ST STM32F038C6
ST STM32F038C6T7
ST STM32F038 6 Series
ST STM32F038G6
ST STM32F038K6
ST STM32F038E6
ST STM32F038G6U6
ST STM32F038F6P6TR
ST STM32F038F6P6
ST STM32F038K6U6
ST Categories
Motherboard
Computer Hardware
Microcontrollers
Control Unit
Controller
More ST Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL