Cpu Filter L3 Control Packet Settings; Single Ip Management - D-Link xStack Reference Manual

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xStack DGS-3200 Series Layer 2 Managed Gigabit Ethernet Switch Web UI Reference Guide

CPU Filter L3 Control Packet Settings

Users can discard and display Layer 3 control packets sent to the CPU from specific ports.
To view the following window, click Configuration > CPU Filter L3 Control Packet Settings:
To set CPU filter Layer 3 control packet settings on the Switch, use the From Port and To Port drop-down menus to select the
desired port range, change the State to Enabled, and tick the desired Layer 3 categories (IGMP Query, DVMRP, PIM, OSPF, RIP,
VRRP, or All). Click Apply when finished.

Single IP Management

Simply put, D-Link Single IP Management is a concept that will stack switches together over Ethernet instead of using stacking
ports or modules. There are some advantages in implementing the "Single IP Management" feature:
1. SIM can simplify management of small workgroups or wiring closets while scaling the network to handle increased
bandwidth demand.
2. SIM can reduce the number of IP address needed in your network.
3. SIM can eliminate any specialized cables for stacking connectivity and remove the distance barriers that typically limit
your topology options when using other stacking technology.
Switches using D-Link Single IP Management (labeled here as SIM) must conform to the following rules:
•
SIM is an optional feature on the Switch and can easily be enabled or disabled through the Command Line Interface or
Web Interface. SIM grouping has no effect on the normal operation of the Switch in the user's network.
•
There are three classifications for switches using SIM. The Commander Switch (CS), which is the master switch of the
group, Member Switch (MS), which is a switch that is recognized by the CS a member of a SIM group, and a
Candidate Switch (CaS), which is a Switch that has a physical link to the SIM group but has not been recognized by the
CS as a member of the SIM group.
•
A SIM group can only have one Commander Switch (CS).
Figure 2 - 46. CPU Filter L3 Control Packet Settings window
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