Xilinx RocketIO User Manual page 4

Product Not Recommended for New Designs
Date Version
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06/12/03 2.1
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11/07/03 2.2
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• Section "Voltage Regulation" in Chapter 3: Added material defining voltage regulator
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• Various non-technical edits and corrections.
RocketIO™ Transceiver User Guide
Table 1-2: Added qualifying footnote to XAUI 10GFC.
Table 1-5: Corrected definition of RXRECCLK.
"RocketIO Transceiver Instantiations" in Chapter
explaining what the Instantiation Wizard does.
Table 2-14: Changed numerics from exact values to rounded-off approximations
(nearest 5,000), and added footnote calling attention to this.
"Clocking" in Chapter
reference clock input to FPGA fabric.
"RXRECCLK" in Chapter
to divide-by-10. (RXRECCLK is always 1/20th the data rate.).
"CRC_FORMAT" in Chapter
USER_MODE to "greater than 20".
Table 3-5: Clarified the significance of the V
"AC and DC Coupling" in Chapter
V /V settings when AC or DC coupling is used.
TRX TTX
Table 4-1: Corrected pinouts for FG256 and FG456.
Table 4-3: Corrected pinouts for FF1517 (XC2VP70).
"Clock Signals" in Chapter
♦
the reference clock must be provided at all times.
♦
any added jitter on the reference clock will be reflected on the RX/TX I/O.
Figure 2-3: Added a BUFG after the IBUFGDS reference clock buffer.
"RX_BUFFER_USE" in Chapter
"RXUSRCLK/RXUSRCLK2".
Table 2-20: Added footnotes qualifying the maximum receive-side latency parameters
given in the table.
"FIBRE_CHAN" in Chapter
(24 bytes not including CRC placeholder).
"ETHERNET" in Chapter
frame specifications must be adhered to.
Table 2-23: Corrected "External" to "Internal" loopback. Improved explanation of
Parallel Mode loopback.
Figure 2-28, "Serial and Parallel Loopback Logic."
"Clock and Data Recovery" in Chapter
RXRECCLK is always 1/20th the incoming data rate, and that CDR requires a
minimum number of transitions to achieve and maintain a lock on the received data.
requirements when a device other than the LT1963 is used.
"AC and DC Coupling" in Chapter
V /V voltage compliance.
TRX TTX
Figure 3-17 and section "Epson EG-2121CA 2.5V (LVPECL Outputs)" in Chapter
Added material specifying the optional use of an LVPECL buffer as an alternative to
the LVDS buffer previously specified.
Table 4-2: Added pinouts for FG676 package, XC2VP20 and XC2VP30.
Table A-5: Added BREFCLK parameters T
"Application Notes" in Appendix
XAPP648, XAPP669, and XAPP670.
www.xilinx.com
Revision
2: added text recommending use of an IBUFGDS for
2: Deleted references to SERDES_10B attribute and
2: Corrected minimum data length for
/V voltages shown in this table.
TTX TRX
3: Explanatory material added regarding
2: Added material that states:
2: Corrected erroneous "USRCLK2" to
2: Added specification for minimum data length
2: Added note indicating that Gigabit Ethernet 802.3
3: Corrected text to make clear that
3: Added footnote to
and T
BREFPWH
C: Included new Xilinx Application Notes
UG024 (v3.0) February 22, 2007
1: added text briefly
Table 3-8 clarifying
3:
.
BREFPWL