Xilinx RocketIO User Manual page 45

Product Not Recommended for New Designs
Clocking
Verilog Template
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
U_DCM: DCM
port map (
CLKIN =>
CLKFB =>
DSSEN =>
PSINCDEC =>
PSEN =>
PSCLK =>
RST =>
CLK0 =>
LOCKED =>
);
--
-- BUFG Instantiation
U_BUFG: IBUFG
port map (
I => REFCLKIN,
O => REFCLK
);
U2_BUFG: BUFG
port map (
I => CLK0_W,
O => USRCLK_M
);
end TWO_BYTE_CLK_arch;
//Module: TWO_BYTE_CLK
//Description: Verilog Submodule
// DCM for 2-byte GT
//
// Device: Virtex-II Pro Family
module TWO_BYTE_CLK (
REFCLKIN,
REFCLK,
USRCLK_M,
DCM_LOCKED
);
input REFCLKIN;
output REFCLK;
output USRCLK_M;
output DCM_LOCKED;
wire REFCLKIN;
wire REFCLK;
wire USRCLK_M;
wire DCM_LOCKED;
wire REFCLKINBUF;
wire clk_i;
DCM dcm1 (
.CLKFB ( USRCLK_M ),
.CLKIN ( REFCLKINBUF ),
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REFCLK,
USRCLK_M,
GND,
GND,
GND,
GND,
RST,
CLK0_W,
LOCK
R
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