Xilinx RocketIO User Manual page 6

Product Not Recommended for New Designs
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02/22/07 3.0
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RocketIO™ Transceiver User Guide
"Example 1a: Two-Byte Clock with DCM," page
TWO_BYTE_CLK definition (VHDL).
"Example 2: Four-Byte Clock," page
(VHDL).
"RX_LOSS_OF_SYNC_FSM," page
attribute values to be valid.
"CRC Operation," page 84: Added CRC logic start state on reset.
"Power Conditioning," page
"Passive Filtering," page 111: Corrected part number of Murata ferrite bead.
"Pletronics LV1145B (LVDS Outputs)," page
LVDS_25_DT.
"Powering the RocketIO Transceivers," page
the Unused RocketIO Transceivers."
"The POWERDOWN Port," page
initializes the PMA.
"HSPICE," page 121 and "Characterization Reports," page
to SPICE Model and Characterization Report web pages.
Figure 2-12: In 8B/10B Data Flow block diagram, moved Comma Detect function
from PMA to PCS.
Table 3-4:
♦
Corrected REFCLK/BREFCLK typical rise/fall time from 400 ps to 600 ps.
♦
Corrected TLOCK acquisition time from Typ to Max.
Table 3-5: Corrected voltage range in heading to 1.6V–1.8V.
Table B-1: Corrected data characters D18.2, D09.3, D10.3, D18.5, and D18.6.
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Revision
43: Corrected code in
46: Corrected code in DCM instantiation
77: Added note that PLL must be locked for
109: Fixed broken link to Data Sheet DS083.
119: Corrected I/O standard name to
120: Added section
120: Added that toggling POWERDOWN properly
"Pin Connections on
149: Fixed obsolete links
UG024 (v3.0) February 22, 2007