Xilinx RocketIO User Manual page 52

Product Not Recommended for New Designs
R
Verilog Template
52
--
signal GND : std_logic;
signal CLK0_W : std_logic;
signal CLK2X180_W : std_logic;
signal USRCLK2_M_W : std_logic;
signal USRCLK_M_W : std_logic;
begin
GND <= '0';
USRCLK2_M <= USRCLK2_M_W;
USRCLK_M <= USRCLK_M_W;
--
-- DCM Instantiation
U_DCM: DCM
port map (
CLKIN =>
CLKFB =>
DSSEN =>
PSINCDEC =>
PSEN =>
PSCLK =>
RST =>
CLK0 =>
CLK2X180 =>
LOCKED =>
);
-- BUFG Instantiation
U_BUFG: IBUFG
port map (
I => REFCLKIN,
O => REFCLK
);
U2_BUFG: BUFG
port map (
I => CLK0_W,
O => USRCLK_M_W
);
U4_BUFG: BUFG
port map (
I => CLK2X180_W,
O => USRCLK2_M_W
);
end ONE_BYTE_CLK_arch;
// Module: ONE_BYTE_CLK
// Description: Verilog Submodule
// DCM for 1-byte GT
// Device: Virtex-II Pro Family
module ONE_BYTE_CLK (
REFCLKIN,
REFCLK,
www.xilinx.com
Chapter 2: Digital Design Considerations
REFCLK,
USRCLK_M,
GND,
GND,
GND,
GND,
RST,
CLK0_W,
CLK2X180_W,
LOCK
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007