Xilinx RocketIO User Manual page 40

Product Not Recommended for New Designs
R
Table 2-1: Clock Ports
BREFCLK
BREFCLK2
RXRECCLK
REFCLK
REFCLK2
REFCLKSEL
RXUSRCLK
TXUSRCLK
RXUSRCLK2
TXUSRCLK2
Notes:
1. TXUSRCLK and TXUSRCLK2 must be driven by clock sources, even if only the receiver of the MGT is
Table 2-2: Reference Clock Usage
REFCLK
BREFCLK
Notes:
1. Because of dedicated routing to reduce jitter, BREFCLK cannot be routed through the fabric.
2. While this option is available in the silicon, this topography adds extra jitter to the reference clock
40
±100 ppm or better, with jitter as low as possible. Module 3 of the Virtex-II Pro data sheet gives
further details.
Clock I/Os
Input Reference clock used to read the TX FIFO and multiplied by
20 for parallel-to-serial conversion (20X)
Input Alternative to BREFCLK
Output Recovered clock (from serial data stream) divided by 20.
Clocks data into the elastic buffer.
Input Reference clock used to read the TX FIFO and multiplied by
20 for parallel-to-serial conversion (20X)
Input Alternative to REFCLK.
Input Selects which reference clock is used. 0 selects REFCLK;
1 selects REFCLK2.
Input Clock from FPGA used for reading the RX Elastic Buffer.
Clock signals CHBONDI and CHBONDO into and out of the
transceiver. This clock is typically the same as TXUSRCLK.
(1)
Input Clock from FPGA used for writing the TX Buffer. This clock
must be frequency locked to REFCLK for proper operation.
Input Clock from FPGA used to clock RX data and status between
the transceiver and FPGA fabric. The relationship between
RXUSRCLK2 and RXUSRCLK depends on the width of the
receiver data path. RXUSRCLK2 is typically the same as
TXUSRCLK2.
(1)
Input Clock from FPGA used to clock TX data and status between
the transceiver and FPGA fabric. The relationship between
TXUSRCLK2 and TXUSRCLK depends on the width of the
transmission data path.
being used.
600 Mb/s –
2.499 Gb/s
√
√
which can affect the overall performance of the transceiver.
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Chapter 2: Digital Design Considerations
Description
Data Rate
2.500 Gb/s –
3.125 Gb/s
√
Routing
Can Route Can Route
Across Chip? Through BUFG?
(2) (2)
√ √
Note (1) Note (1)
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007