Index - Xilinx RocketIO User Manual

Product Not Recommended for New Designs

Index

Numerics
8B/10B Encoding/Decoding
bypassing 66
60
decoder
60
encoder
60
overview
ports and attributes 61
serial output format 66
135
8B/10B Valid Characters
A
117
AC and DC Coupling
Attributes & Ports (by function)
8B/10B encoding/decoding
90
buffers, fabric interface
81
channel bonding
73
clock correction
CRC 85
SERDES alignment 67
76
synchronization logic
Attributes (defined)
67
ALIGN_COMMA_MSB
CHAN_BOND__SEQ_LEN
CHAN_BOND_LIMIT 82
81
CHAN_BOND_MODE
CHAN_BOND_OFFSET
CHAN_BOND_ONE_SHOT
CHAN_BOND_SEQ_*_*
CHAN_BOND_SEQ_2_USE
82
CHAN_BOND_WAIT
CLK_COR_INSERT_IDLE_FLAG
75
75
CLK_COR_KEEP_IDLE
CLK_COR_REPEAT_WAIT
CLK_COR_SEQ_*_* 74
75
CLK_COR_SEQ_LEN
73
CLK_CORRECT_USE
70
COMMA_10B_MASK
CRC_END_OF_PACKET
CRC_FORMAT 85
CRC_START_OF_PACKET
DEC_MCOMMA_DETECT
DEC_PCOMMA_DETECT
DEC_VALID_COMMA_ONLY
MCOMMA_10B_VALUE
70
MCOMMA_DETECT
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
PCOMMA_10B_VALUE
PCOMMA_DETECT
PRE_EMPHASIS
RX_BUFFER_USE
RX_CRC_USE
RX_DATA_WIDTH
RX_DECODE_USE
RX_LOS_INVALID_INCR
RX_LOS_THRESHOLD
RX_LOSS_OF_SYNC_FSM
SERDES_10B
TERMINATION_IMP
TX_BUFFER_USE
TX_CRC_FORCE_VALUE
TX_CRC_USE
61
TX_DATA_WIDTH
TX_DIFF_CTRL
Attributes (table)
B
BREFCLK
and REF_CLK_V_SEL
and REFCLKSEL
81
and serial speed
pin numbers
when & how to use
82
Buffers, Fabric Interface
81
ports and attributes
81
transmitter and elastic (receiver)
81
Byte Mapping
C
Channel Bonding (Alignment)
75
operation
ports and attributes
troubleshooting
Vitesse channel bonding sequence
receive
88
transmit
Characters, valid (tables)
88
Clock Correction (Recovery)
70
clock recovery
70
overview
70
ports and attributes
70
Clock/Data Recovery (CDR) parameters
108
www.xilinx.com
70
70
91
74 90
,
85
90
61
77
77
77
90
91
90
89
85
90
91
29
32 41
,
25 41
,
39
41
41
89
90
89
38
79
80
81
83
65
64
135
72
71
73
39
Clocking
72
clock and data recovery
clock correction (recovery)
clock dependency 56
clock descriptions 127
130
clock pulse width
42
clock ratio
72
clock recovery
clock signals 39
clock synthesizer 71
129
clock-to-output delays
code examples
50
1-byte clock
2-byte clock 43
4-byte clock 46
half-rate clocking scheme
multiplexed clocking scheme
55
with DCM
without DCM 55
Control Characters, valid (table)
117
Coupling, AC and DC
CRC (Cyclic Redundancy Check)
84
generation
latency 85
84
operation
85
ports and attributes
89
support limitations
D
Data Characters, valid (table)
Data Path Latency 57
67
Deserializer
108
Deterministic Jitter (DJ)
107
Differential Receiver
Differential Trace Design 116
H
54
Half-Rate Clocking Scheme
HDL Code Examples
Verilog
1-byte clock 52
2-byte clock 45
32-bit alignment design
49
4-byte clock
VHDL
1-byte clock 50
71
54
143
84
135
95
153