Xilinx RocketIO User Manual page 47

Product Not Recommended for New Designs
Clocking
any interface logic. Both USRCLK and USRCLK2 are aligned on the falling edge, since
USRCLK_M is 180° out of phase when using local inverters with the transceiver.
Clocks for 4-Byte Data Path
VHDL Template
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Note:
These local MGT clock input inverters, shown and noted in
in the FOUR_BYTE_CLK templates.
REFCLK
REFCLK_P
TXUSRCLK
REFCLK_N
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
Figure 2-4: Four-Byte Clock
-- Module: FOUR_BYTE_CLK
-- Description: VHDL submodule
-- DCM for 4-byte GT
--
-- Device: Virtex-II Pro Family
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity FOUR_BYTE_CLK is
port (
REFCLKIN : in std_logic;
RST : in std_logic;
USRCLK_M : out std_logic;
USRCLK2_M : out std_logic;
REFCLK : out std_logic;
LOCK : out std_logic
);
end FOUR_BYTE_CLK;
--
architecture FOUR_BYTE_CLK_arch of FOUR_BYTE_CLK is
--
-- Components Declarations:
component BUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
--
component IBUFG
port (
www.xilinx.com
MGT + DCM for 4-Byte Data Path
CLKDV_DIVIDE = 2
IBUFGDS
DCM
CLKIN CLKDV
CLKFB
RST
CLK0
Figure 2-4, are not included
GT_std_4
0 REFCLKSEL
BUFG
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
MGT clock input invert-
BUFG
ers (acceptable skew)
UG024_03_112202
47
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