Xilinx RocketIO User Manual page 94

Product Not Recommended for New Designs
R
Table 2-24: 32-bit RXDATA, Aligned versus Misaligned
32-bit aligned
CHARISCOMMA
32-bit misaligned
CHARISCOMMA
When RXDATA is 32-bit aligned, the logic should pass RXDATA though to the protocol
logic without modification. A properly aligned data flow is shown in
When RXDATA is 32-bit misaligned, the word requiring alignment is split between
consecutive RXDATA words in the data stream, as shown in
in the figure refers to the design example code in
This conditional shift/delay operation on RXDATA also must be performed on the status
outputs RXNOTINTABLE, RXDISPERR, RXCHARISK, RXCHARISCOMMA, and
RXRUNDISP in order to keep them properly synchronized with RXDATA.
It is not possible to adjust RXCLKCORCNT appropriately for shifted/delayed RXDATA,
because RXCLKCORCNT is summary data, and the summary for the shifted case cannot
be recalculated.
94
RXDATA
[31:24]
TXDATA
BC95B5B5
RXDATA
BC95B5B5
ALIGNED_DATA
pppppppp
Figure 2-29: RXDATA Aligned Correctly
TXDATA
BC95B5B5
RXDATA
pppp BC95
RXDATA_REG[15:0]
ALIGNED_DATA pppppppp
Figure 2-30: Realignment of RXDATA
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Chapter 2: Digital Design Considerations
RXDATA RXDATA
[23:16]
BC 95
1 0
pp pp
0 0
FDB53737 45674893
FDB53737 45674893
BC95B5B5 FDB53737
"32-bit Alignment Design," page
FDB53737 45674893
B5B5FDB5 37374567
pppp BC95 FDB5
pppppppp
BC95B5B5
RXDATA
[15:8] [7:0]
B5 B5
0 0
BC 95
1 0
Figure 2-29.
nnnnnnnn nnnnnnnn
nnnnnnnn nnnnnnnn
45674893 nnnnnnnn
ug024_33_091602
Figure 2-30. (RXDATA_REG
nnnnnnnn nnnnnnnn
4893 nnnn nnnnnnnn
4567 nnnn
FDB53737 45674893
ug024_34_091602
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
95.)