Xilinx RocketIO User Manual page 5

Product Not Recommended for New Designs
Date Version
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02/24/04 2.3
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• Section
• Section
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• Section "Voltage Regulation" in Chapter 3: Added Linear Technology part numbers
• Section
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• Changed the value of TRCLK/RFCLK in
05/20/04 2.3.1
• Modified
06/24/04 2.3.2
• Fixed error in Hex value in
08/25/04 2.4
• Add application notes to
• Replaced "Voltage Regulation" section with
• Removed all references to the XCVP125 device.
• Modified Note 4 in
• Added PCI Express and new note to
12/09/04 2.5
• Fixed typo in
• Added XAPP572 to
UG024 (v3.0) February 22, 2007
Table 2-3, page 41: Added FG676 row to BREFCLK Pin Numbers.
Figure 2-4, page 47: Added note above Figure 2-4 stating, "These local MGT clock
input inverters, shown and noted in Figure 2-4, are not included in the
FOUR_BYTE_CLK templates.
Section"RXRECCLK" in Chapter
RXRECCLK changes monotonically and how the recovered bit clock is derived.
"Data Path Latency" in Chapter
many configurations of the MGT, both the transmit and receive data path latencies
vary."
"RXBUFSTATUS" in Chapter
Figure 3-1, page 103: Replaced old Figure 3-1, page 101, with new
"Differential Amplifier."
Figure 3-6, page 107: Added new Figure 3-6, page 105, showing "MGT Receiver."
Table 3-4, page 108: Added text to CDR Parameters (TLOCK parameter in Conditions
column) and edited Note 3.
(LT1963A, LT1964).
"Passive Filtering" in Chapter
transceiver.
Figure 3-8, page 111: Replaced old Figure 3-8 with new figure showing "Power
Filtering Network on Devices with Internal and External Capacitors."
Table 3-7, page 112: Added Device and Package combinations table.
Figure 3-9, page 113: Added new Figure 3-10, page 110, showing "Example Power
Filtering PCB Layout for Four MGTs, in Device with Internal Capacitors, Bottom
Layer." Modified the text describing
Figure 3-10, page 114: Replaced old Figure 3-10 with new figure showing "Example
Power Filtering PCB Layout for Four MGTs, in Device with External Capacitors, Top
Layer." Removed the text describing old Figure 3-10.
Figure 3-11, page 115: Replaced old Figure 3-11 with new figure showing "Example
Power Filtering PCB Layout for Four MGTs, in Device with External Capacitors,
Bottom Layer." Removed the text describing old Figure 3-11.
Table 3-8, page 118: Added V
environments.
Figure 2-3.
Appendix C, "Related Online Documents."
"Voltage Regulator Selection and Use" in Chapter
Table 3-5.
in Table 1-5. Updated Table
"Epson EG-2121CA 2.5V (LVPECL Outputs)," page
Appendix C, "Related Online Documents"
to XAPP572 inTable 1-6 (under SERDES_10B description) and
Scheme," page 54.
www.xilinx.com
Revision
2: Added paragraph to section explaining how
2: Revised first sentence to read: "With the
2: Revised the description of RXBUFSTATUS.
3: Added new cap rules for RocketIO
Figure 3-9, page
and V voltages for different coupling
TRX TTX
Table 3-4.
Table 2-15, page 74.
3.
Table 1-2. Added sentence to REFCLK definition
3-5.
RocketIO™ Transceiver User Guide
Figure 3-1 showing
113.
119.
and added references
"Half-Rate Clocking