Xilinx RocketIO User Manual page 132

Product Not Recommended for New Designs
R
Table A-4: Parameters Relative to the TX User Clock2 (TXUSRCLK2) (Continued)
Parameter
T _TRST/T _TRST
GCCK GCKC
T _TKCH/T _TKCH
GCCK GCKC
T _TCDM/T _TCDM
GCCK GCKC
T _TCDV/T _TCDV
GCCK GCKC
T _CFGIN/T _CFGIN
GDCK GCKD
T _TDAT/T _TDAT
GDCK GCKD
Clock to Out:
T _TBERR
GCKST
T _TKERR
GCKST
T _TRDIS
GCKDO
T _CFGOUT
GCKDO
Clock:
T
TX2PWH
T
TX2PWH
Table A-5: Miscellaneous Clock Parameters
Parameter
Clock:
T
REFPWH
T
REFPWL
T
BREFPWH
T
BREFPWL
T
TX2PWH
T
TX2PWL
Notes:
1. REFCLK is not synchronous to any RocketIO signals.
2. BREFCLK is not synchronous to any RocketIO signals.
3. TXUSRCLK is not synchronous to any RocketIO signals.
132
Appendix A: RocketIO Transceiver Timing Model
Function
Control inputs
Control inputs
Control inputs
Control inputs
Data inputs
Data inputs
Status outputs
Status outputs
Data outputs
Data outputs
Clock pulse width, High state
Clock pulse width, Low state
Function
Clock pulse width, High state
Clock pulse width, Low state
Clock pulse width, High state
Clock pulse width, Low state
Clock pulse width, High state
Clock pulse width, Low state
www.xilinx.com
Signals
TXRESET
TXCHARISK[3:0]
TXCHARDISPMODE[3:0]
TXCHARDISPVAL[3:0]
CONFIGIN
TXDATA[31:0]
TXBUFERR
TXKERR[3:0]
TXRUNDISP[3:0]
CONFIGOUT
TXUSRCLK2
TXUSRCLK2
Signals
(1)
REFCLK
(1)
REFCLK
(2)
BREFCLK
(2)
BREFCLK
(3)
TXUSRCLK
(3)
TXUSRCLK
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007