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RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
The following table shows the revision history for this document.
Date
Version
• Initial Xilinx release.
11/20/01
1.0
• Updated for typographical and other errors found during review.
01/23/02
1.1
• Part of Virtex-II Pro™ Developer's Kit (March 2002 Release)
02/25/02
1.2
• Updated
07/11/02
1.3
• Added additional IMPORTANT NOTE regarding ISE revisions at the beginning of
09/27/02
1.4
• Added material in section
• Added section
• New pre-emphasis eye diagrams in section
• Numerous parameter additions previously shown as "TBD" in
• Corrected pinouts for FF1152 package, device column 2VP20/30, LOC Constraints
10/16/02
1.5
• Corrected section
• Corrected sequence of packet elements in
11/20/02
1.6
• Corrected max PCB drive distance to 40 inches.
• Reorganized content sequence in
• Code corrections in VHDL Clock templates.
• Corrections in clocking scheme drawings. Addition of drawings showing clocking
• Corrections made to power regulator schematic,
• Added clarifying text regarding trace length vs. width.
12/12/02
1.6.1
• Reorganized existing content
03/25/03
2.0
• Added new content
• Added
• Added
UG024 (v3.0) February 22, 2007
"PCB Design
Requirements". Added
Timing Model."
Changed Cell Models to Appendix B.
Chapter 1
"Other Important Design Notes."
rows GT_X0_Y0 and GT_X0_Y1.
"CRC Latency"
TXUSRCLK and RXUSRCLK cycles.
Table
1-2: Added support for XAUI Fibre Channel.
Table
1-5: Additional information in RXCOMMADET definition.
"Data Path Latency"
section expanded and reformatted.
schemes without using DCM.
Table
B-1: Corrections in Valid Data Characters.
Table
3-4: Data added.
Table
2-23: Data added/corrected.
Appendix C, "Related Online Documents"
"Index"
www.xilinx.com
Revision
Appendix A, "RocketIO Transceiver
"CRC (Cyclic Redundancy Check)."
"Pre-emphasis Techniques."
and
Table 2-20
to express latency in terms of
Figure
2-30.
Chapter 2, "Digital Design Considerations."
Figure
RocketIO™ Transceiver User Guide
"MGT Package Pins."
3-7.

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