Xilinx RocketIO User Manual page 154

Product Not Recommended for New Designs
R
43
2-byte clock
32-bit alignment design
4-byte clock 47
High-Speed Serial Trace Design
121
HSPICE
I
Implementation Tools 121
J
Jitter
41
and BREFCLK
and use of DCM with REFCLK
deterministic and random, defined
107
parameters 107 108
,
PCB trace length mismatch
K
143
K-Characters, valid (table)
L
Latency, Data Path 57
M
90
Miscellaneous Signals
34
Modifiable Primitives (table)
Multiplexed Clocking Scheme
with DCM 55
55
without DCM
P
123
Package Pins
Par 121
Passive Filtering 111
109
PCB Design Requirements
Ports & Attributes (by function)
8B/10B encoding/decoding
buffers, fabric interface 90
channel bonding 81
73
clock correction
85
CRC
67
SERDES alignment
synchronization logic 76
Ports (defined)
154
CHBONDDONE
98
CHBONDI
CHBONDO
115
ENCHANSYNC
ENMCOMMAALIGN
ENPCOMMAALIGN
LOOPBACK
POWERDOWN
RXBUFSTATUS
RXCHARISCOMMA
RXCHARISK
RXCHECKINGCRC
RXCLKCORCNT
RXCOMMADET
RXCRCERR
39
RXDISPERR
RXLOSSOFSYNC
RXNOTINTABLE
115
RXPOLARITY
RXREALIGN
RXRECCLK
RXRUNDISP
TXBUFERR
TXBYPASS8B10B
TXCHARDISPMODE
TXCHARDISPVAL
TXCHARISK
TXFORCECRCERR
TXINHIBIT
63
TXKERR
TXPOLARITY
TXRUNDISP
Ports (table) 24
Power Supply
passive filtering
power conditioning
Power Supply Circuit Using Approved
Regulator (figure)
Pre-emphasis
available values
104
overview
scope screen captures
Q
61
Qualified Linear Regulators (table)
R
Random Jitter (RJ)
Receive Data Path 32-bit Alignment
89
Receiver Buffer
www.xilinx.com
83
Reference Clock
83
83
81
68
Reset/Power Down
68
RocketIO transceiver
91
120
90
71
63
88
76 83
,
71
88
64
77 83
,
64
91
70
56
63
90
61
62
62
63
89
91
91
63
111
109
Routing Serial Traces
110
S
104
SERDES Alignment
105 106
,
Serial I/O Description
Serializer
110
Setup/Hold Times of Inputs Relative to
Simulation Models
SmartModels
108
Synchronization Logic
93
119
generating
oscillator (Epson), for LVPECL
oscillator (Pletronics), for LVDS
57
additional resources 18
analog design considerations
145
application notes
29
attributes (table)
basic architecture and capabilities
block diagram 22 128
,
channel bonding (channel align-
ment) 79
characterization reports 149
39
clocking
communications standards support-
21
ed
CRC (Cyclic Redundancy Check)
default attribute values (tables)
design notes
120
analog
93
digital
digital design considerations
modifiable primitives 34
number of MGTs per device type
109
PCB design requirements
24
ports (table)
120
powering
related online documents 145
reset/power down 57
simulation and implementation
120
unused transceivers
valid control characters (K-charac-
143
ters)
valid data characters 135
white papers 151
115
overview 67
ports and attributes 67
103
67
129
Clock
121
121
76
overview
76
ports and attributes
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
119
119
103
21
84
34
39
21
121