Xilinx RocketIO User Manual page 44

Product Not Recommended for New Designs
R
44
RST : in std_logic;
USRCLK_M : buffer std_logic;
REFCLK : buffer std_logic;
LOCK : out std_logic
);
end TWO_BYTE_CLK;
--
architecture TWO_BYTE_CLK_arch of TWO_BYTE_CLK is
--
-- Components Declarations:
component BUFG
port (
I: in std_logic;
O : out std_logic
);
end component;
--
component IBUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
--
component DCM
port (
CLKIN : in std_logic;
CLKFB : in std_logic;
DSSEN : in std_logic;
PSINCDEC : in std_logic;
PSEN : in std_logic;
PSCLK : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector ( 7 downto 0 )
);
end component;
--
-- Signal Declarations:
--
signal GND : std_logic;
signal CLK0_W : std_logic;
begin
GND <= '0';
--
-- DCM Instantiation
www.xilinx.com
Chapter 2: Digital Design Considerations
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007