Xapp649: Sonet Rate Conversion In Virtex-Ii Pro Devices; Xapp651: Sonet And Otn Scramblers/Descramblers; Xapp652: Word Alignment And Sonet/Sdh Deframing; And Differential Swing Control Attributes - Xilinx RocketIO User Manual

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a backplane bus. Utilization of a hardware test-and-set lock mechanism, along with a
software protocol to test for a semaphore grant prior to accessing the shared memory,
guarantees atomic access to the shared memory.

XAPP649: SONET Rate Conversion in Virtex-II Pro Devices

The RocketIO transceivers have several modes of operation, but all modes rely on the
internal transmitter clock being multiplied by 20 for data transmission. For example, a
20-bit data stream passed to the unit at 125 MHz is serialized and retransmitted at
2.5 Gb/s. At a 156.25 MHz input, the output is at its maximum speed of 3.125 Gb/s. The
parallel data stream applied to the RocketIO transceiver can either be 20 bits direct, or it
can be written as 16 bits, to which 8b/10b coding is applied to generate the 20 bits required.
However, there is a class of applications, typically in SONET processing systems, where
the data path is 16 bits wide, running at 155.52 MHz. The designer would ideally apply the
data directly to the RocketIO transceiver for onward transmission at 155.52 x 16 =
2.48832 Gb/s. Since this cannot be done in Virtex-II Pro devices, this application note
describes the logic necessary to perform this function.
This application note is divided into two sections, the first is the logic necessary for the
data width conversion, and the second describes the clocking characteristics required by
the RocketIO transceiver.

XAPP651: SONET and OTN Scramblers/Descramblers

Both SONET and OTN are standards for data transmission over fibre optic links. This
implies a need for clock recovery at the receiver, which in turn requires a guaranteed
minimum number of transitions in the incoming serial data stream. The mechanism to
achieve this transition density, similar for both SONET and OTN, is known as scrambling.
The scrambling (and descrambling) function is independent of the serial data rate used.
Serial data for transmission is added to the output of a pseudo-random number generator,
running at the same clock frequency. The same circuit is used in the receiver to recover the
original data transmitted. Obviously, the pseudo-random number generators at each end
of the link must be in phase. This is achieved using a known pattern of framing
information (which is actually transmitted unscrambled). This is covered in more detail in
XAPP652.

XAPP652: Word Alignment and SONET/SDH Deframing

This application note describes the logic to perform basic word alignment and deframing
specifically for SONET/SDH systems, where data is being processed at 16 bits or 64 bits
per clock cycle.
XAPP660: Partial Reconfiguration of RocketIO Pre-emphasis

and Differential Swing Control Attributes

This application note describes a pre-engineered solution for Virtex-II Pro devices using
the IBM PowerPC™ 405 core to perform a partial reconfiguration of the RocketIO™ multi-
gigabit transceivers (MGTs) pre-emphasis and differential swing control attributes. This
solution is ideal for applications where these attributes must be modified to optimize the
MGT signal transmission for various system environments while leaving the rest of the
FPGA design unchanged. The hardware and software elements of this solution can be
easily integrated into any Virtex-II Pro design. The associated reference design supports
the following devices: XC2VP4, XC2VP7, XC2VP20, and XC2VP50. The design discussed
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Appendix C: Related Online Documents
www.xilinx.com RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007