Xilinx RocketIO User Manual page 53

Product Not Recommended for New Designs
Clocking
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
USRCLK_M,
USRCLK2_M,
DCM_LOCKED
);
input REFCLKIN;
output REFCLK;
output USRCLK_M;
output USRCLK2_M;
output DCM_LOCKED;
wire REFCLKIN;
wire REFCLK;
wire USRCLK_M;
wire USRCLK2_M;
wire DCM_LOCKED;
wire REFCLKINBUF;
wire clk_i;
wire clk_2x_180;
DCM dcm1 (
.CLKFB
.CLKIN
.DSSEN
.PSCLK
.PSEN
.PSINCDEC
.RST
.CLK0
.CLK90
.CLK180
.CLK270
.CLK2X
.CLK2X180
.CLKDV
.CLKFX
.CLKFX180
.LOCKED
.PSDONE
.STATUS
);
BUFG buf1 (
BUFG buf2 (
IBUFGbuf3 (
endmodule
www.xilinx.com
( USRCLK_M ),
( REFCLKINBUF),
( 1'b0 ),
( 1'b0 ),
( 1'b0 ),
( 1'b0 ),
( 1'b0 ),
( clk_i ),
( ),
( ),
( ),
( ),
( clk2x_180 ),
( ),
( ),
( ),
( DCM_LOCKED ),
( ),
( )
.I ( clk2x_180 ),
.O ( USRCLK2_M )
);
.I ( clk_i ),
.O ( USRCLK_M )
);
.I ( REFCLKIN ),
.O ( REFCLKINBUF )
);
R
53