Fujitsu F2MC-8L F202RA Hardware Manual page 183

● Count clock selectors 0/1
Circuits that select input clocks. In timer 0 for the 8-bit mode or in the 16-bit mode, count clock selector 0/
1 can select seven internal clocks and one external clock. In timer 1 for the 8-bit mode, the selector can
select only seven internal clocks.
● Counter circuits 0/1
Counter circuit 0 and counter circuit 1 each consist of an 8-bit counter, a comparator, a comparator data
latch, and data registers (TDR0, TDR1).
The 8-bit counter is incremented according to the selected count clock and clock edge (rising/falling). The
comparator compares the counter value with the comparator data latch value. When these values match, the
counter is cleared and the data register value is set in (loaded to) the comparator data latch.
In the 8-bit mode, counter circuits 0 and 1 operate independently as timer 0 and timer 1, respectively. In the
16-bit mode, counter circuits 0 and 1 operate as the 16-bit counter in which counter circuit 0 is
concatenated as lower 8 bits and counter circuit 1 is concatenated as higher 8 bits.
● Square wave output control circuit
When the comparator detects that the counter value matches the comparator data latch value in the 8- or 16-
bit mode, an interrupt request is generated. In this case, if square wave output is allowed, the corresponding
output control circuit inverts the output of the square wave output pin.
● Timer 0/1 data registers (TDR0, TDR1)
TDR0 and TDR1 are used to set the data to be compared with each 8-bit counter value at write.
● Timer 0/1 control registers (TCR0, TCR1)
TCR0 and TCR1 are used to select functions, allow and prohibit operations, control interrupts, and check
interrupt states.
● 8/16-bit capture timer/counter interrupt
IRQ3: If the interrupt request output is allowed when the counter value equals the value set in the data
register in the interval timer or counter function, an IRQ3 interrupt request is generated. (In timer 0
for the 8-bit mode or in the 16-bit mode, the interrupt request output is allowed when TCR0:
T0IEN=1. In timer 1 for the 8-bit mode, the interrupt request output is allowed when TCR1: T1IEN =1.)
● 8/16-bit capture counter interrupt
IRQ4: If the interrupt request output is allowed each time a capture input edge is detected, an IRQ4
interrupt request is generated. (In timer 0 for the 8-bit mode or in the 16-bit mode, the interrupt
request output is allowed when TCCR: TCEN=1.)
● Capture data registers (TCPL, TCPH)
TCPL and TCPH store the number of events detected in the capture mode.
When capture data is read in the timer mode, the counter value is also read.
● Timer output control register (TCR2)
TCR2 is used to allow and prohibit square wave output and select timer 0 output/timer 1 output.
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
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