Fujitsu F2MC-8L F202RA Hardware Manual page 324

CHAPTER 13 UART
Figure 13.6-5 Operations in Operating Mode 0, 1, or 3 when the Overrun Error Occurs
Data
RDRF=1
(reception buffer full)
ORFE
Reception interrupt
Figure 13.6-6 Operations in Operating Mode 0, 1, or 3 when the Framing Error Occurs
Data
RDRF=0
ORFE
Reception interrupt
Note:
After initialization is cancelled due to a reset, time for 11 shift-clock cycles is required to initialize the
internal controller. Therefore, be sure to enable the UART prescaler operation (PREN = 1) using the
oscillation frequency register after a reset.
308
START 0 1 2
0 1 2
START
3 4 5 6
3 4 5 6
7
STOP
7
STOP