Clock Divider Selection Register (Upc) - Fujitsu F2MC-8L F202RA Hardware Manual

13.4.6

Clock Divider Selection Register (UPC)

The clock divider selection register is used to generate the UART reference clock by
dividing the oscillation frequency. It also enables/disables operation of the prescaler for
creating the reference clock.
■
Clock Divider Selection Register (UPC)
Address bit7 bit6
002C
H
R/W
: Readable/Writable
: Unused
: Initial value
Figure 13.4-8 Clock Divider Selection Register (UPC)
bit5 bit4 bit3 bit2
PREN PR2
R/W R/W
PR2
0
0
0
0
1
1
1
1
PREN
0
1
bit1 bit0 Initial value
----0010
PR1
PR0
R/W R/W
PR1
PR0
0 0
Divides the clock by 1.
0 1 Divides the clock by 2.
Divides the clock by 2.5.
1 0
1 1 Divides the clock by 3.
0 0 Divides the clock by 4.
Divides the clock by 5.
0 1
Do not specify this setting.
1 0
Do not specify this setting.
1 1
UART prescaler operation enable bit
Disables the prescaler operation.
Enables the prescaler operation.
CHAPTER 13 UART
B
Clock divider selection bits
Divider
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