Fujitsu F2MC-8L F202RA Hardware Manual page 298

CHAPTER 13 UART
1
=
Value of baud rate
Notes:
The baud rate is specified using the clock gear register (CS1 and CS0), clock divider registers (PR2,
PR1, and PR0), or baud rate selection registers (RC2, RC1, and RC0). For the example of calculating
the baud rate, see Table 13.1-2 .
• Asynchronous transfer mode
1/12019bps= 0.8 µs{4/F
8(asynchronous) × 1(RC2=RC1=RC0=0) × 13(asynchronous)
• Synchronous transfer mode
1/1.25Mbps = 0.8 µs{4/F
1(synchronous) × 1(RC2=RC1=RC0=0) × 1(synchronous)
Table 13.1-3 provides an example of the baud rates selectable when an external clock is used.
Table 13.1-3 Transfer Cycles and Transfer Rates Selectable for an External Clock
Asynchronous transfer mode
Divider for baud
Transfer cycle
rate
256/F
CR=0 16
1024/F
CR=1 64
*: The minimum value of F
F : Oscillation frequency
CH
Figure 13.1-3 Example of Calculating the Baud Rate (when an External Clock is Selected)
282
Figure 13.1-2 Example of Calculating the Baud Rate
Clock divider
Clock gear
selected
selected
(PR2,PR1,PR0)
4/F , 8/F
CH CH
Divided by 1, 2,
16/ , 64/
F F
CH CH
2.5, 3, 4, or 5
× 2.5(PR2=0,PR1=1,PR0=0)} × 1(CS1=CS0=1) ×
CH
× 2.5(PR2=0,PR1=1,PR0=0)} × 1(CS1=CS0=1) ×
CH
Transfer rate
(bps) *
or more
48828 or less
CH
or more
12207 or less
CH
specified for 12.5 MHz is external clock cycle 16/F
CH
1
Value of baud rate
F
: Oscillation frequency
CH
Baud rate
selected
(RC2,RC1,RC0)
Divided by 1, 2,
4, 8, 16, or 32
Synchronous transfer mode
Divider for
baud rate
1
External clock input
CR CR=0
(min: 8/F
2)
CH
Synchronous/
asynchronous
mode selected
(SMDE)
Divided by 1,
Divided by 1 or
or 8
13
Note: When RC2 is
1 and RC1 is 1, the
divider is 1.
Transfer rate
Transfer cycle
16/F or more
781 k or less
CH
= 1.28 µs.
CH
16
CR=1
64
Clock rate
(CR)
(bps) *