Configuration Of Watchdog Timer - Fujitsu F2MC-8L F202RA Hardware Manual

6.2

Configuration of Watchdog Timer

The watchdog timer consists of the following four function blocks.
• Watchdog timer counter
• Reset control circuit
• Counter clear control circuit
• Watchdog control register (WDTC)
■
Block Diagram of Watchdog Timer
Watchdog control register (WDTC)
22
2 /F
CH
(Time-
base timer
output)
● Watchdog timer counter (1-bit counter)
A 1-bit counter that operates by accepting output from the time-base timer as the count clock.
● Reset control circuit
Sends the reset signal to the CPU when the watchdog timer counter overflows.
● Counter clear control circuit
Controls the clearing and stopping of the watchdog timer counter.
● Watchdog control register (WDTC)
Activates and clears the watchdog timer counter. Because this register is write-only, bit manipulation
instructions cannot be used.
Figure 6.2-1 Block Diagram of Watchdog Timer
WTE3 WTE2
Watchdog timer
Clear
1-bit counter
CHAPTER 6 WATCHDOG TIMER
WTE1 WTE0
Start
Overflow
Reset
control
RST
circuit
129