Fujitsu F2MC-8L F202RA Hardware Manual page 236

CHAPTER 9 12-BIT PPG TIMER
Figure 9.5-2 illustrates the operation of the 12-bit PPG timer.
Count by counter
Cycle period setting
(RCR23, 24:SCL0 to SCL11)
(RCR21, 22:HSC0 to HSC11)
PPG output pulse waveform
If internal count clock cycle period is 2, 4, 16, or 256 t
*1:
period multiplied by the count clock cycle period.
If internal count clock cycle period is 2, 4, 16, or 256 t
*2:
width multiplied by the count clock cycle period.
220
Figure 9.5-2 Operation of 12-bit PPG Timer
"H" width setting
"000 "
H
Cycle period (*1)
(*2)
"H" width
, cycle period = compare value for cycle
INST
, "H" width = compare value for the "H"
INST