Fujitsu F2MC-8L F202RA Hardware Manual page 95

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Block Diagram of Port 0
Note:
When the A/D converter is used, deselect pull-up action for pins P03/INT23/AN7 to P00/INT20/AN4.
Pins set to be used as analog input pins must not be used as an output port.
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Registers PDR0, DDR0, and PUL0 of Port 0
Registers PDR0, DDR0, and PUL0 are associated with port 0.
The bits of these registers correspond to the pins of port 0 in one-to-one correspondence.
Table 4.2-2 tabulates the correspondence between the pins and the bits of the port 0 registers.
Table 4.2-2 Correspondence between the Pins and the Bits of the Port 0 Registers
Port name
PDR0, DDR0, PUL0
Port 0
Pin corresponding to bit
Figure 4.2-1 Block Diagram of Port 0
To A/D
converter's
analog input
PDR
PDR read
PDR read
(when read-modify-write is
performed)
Output latch
PDR write
DDR
DDR write
Stop mode
(SPL=1)
PUL read
PUL
PUL write
SPL: Pin status setting bit of standby control register (STBC)
Bits of associated registers and corresponding pins
bit7
P07
A/D converter A/D converter
channel select enable bit
External
interrupt
External
interrupt
Pch
Nch
bit6 bit5 bit4
P06 P05 P04
CHAPTER 4 I/O PORTS
A/D input occurring
From external
interrupt enable
Stop mode
(SPL=1)
No A/D input
Pull-up
resistor
Pins
bit3 bit2 bit1
P03 P02 P01
bit0
P00
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