Fujitsu F2MC-8L F202RA Hardware Manual page 256

CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
Figure 10.6-2 shows the operation when an external interrupt is input to the INT10 pin.
Pulse waveform
input to INT10 pin
Cleared when EIE0 bit
is set
EIR0 bit
EIE0 bit
SL01 bit
SL00 bit
IRQ0
Note:
Even when the pin is used as an external interrupt input pin, the pin state can be read directly from the
port data register (PDR3).
240
Figure 10.6-2 Operation of External Interrupt 1 (INT10)
Cleared by
program
Edge detection
Rising edge
OFF
Interrupt request flag bit is
cleared by the program
Falling edge Both edges