Fujitsu F2MC-8L F202RA Hardware Manual page 432

INDEX
T
TBTC
Time-base Timer Control Register (TBTC)......... 119
TCCR
Capture Control Register (TCCR) ...................... 171
TCPH and TCPL
Capture Data Registers H and L (TCPH and TCPL)
.......................................................... 182
TCR
Timer 0 Control Register (TCR0) ...................... 173
Timer 1 Control Register (TCR1) ...................... 175
Timer Output Control Register (TCR2) .............. 177
TDR
Timer 0 Data Register (TDR0) .......................... 178
Timer 1 Data Register (TDR1) .......................... 180
Theory
Theory of Operation for Operating Mode 0,1,2, and 3
.......................................................... 305
Time-base Timer
Block Diagram of Time-base Timer ................... 118
Notes on Using Time-base Timer....................... 124
Operations of Interval Timer Function
(Time-base Timer)............................... 122
Operations of Time-base Timer ......................... 122
Oscillation Stabilization Time and Time-base Timer
Interrupts............................................ 121
Programming Examples for Time-base Timer
.......................................................... 125
Register and Vector Table Related to Interrupts from
Time-base Timer ................................. 121
Time-base Timer Control Register
Time-base Timer Control Register (TBTC)......... 119
Timer 0 Control Register
Timer 0 Control Register (TCR0) ...................... 173
Timer 0 Data Register
Timer 0 Data Register (TDR0) .......................... 178
Timer 1 Control Register
Timer 1 Control Register (TCR1) ...................... 175
Timer 1 Data Register
Timer 1 Data Register (TDR1) .......................... 180
Timer Output Control Register
Timer Output Control Register (TCR2) .............. 177
t
INST
Instruction Cycle (t
INST
Transfer
Transfer Instructions......................................... 392
Transfer Clock Rate
Choice of the Transfer Clock Rate ..................... 281
Transferred Data Format
Transferred Data Format ................................... 304
Transition
Diagram for State Transition in Standby Mode
............................................................ 68
416
) ..................................... 57
Transition to Standby Mode and Interrupt ............ 70
Transmission
Transmission Interrupt...................................... 303
Transmission Operations
Transmission Operations in Operating Mode is
0,1,2,or 3............................................ 306
U
UART
Block Diagram of the UART-relating Pins
......................................................... 288
Block Diagram of UART.................................. 284
Functions of UART.......................................... 280
Program Example for UART............................. 311
UART Relating Pins ........................................ 287
UART-relating Registers .................................. 289
UART Interrupt Related Registers
UART Interrupt Related Registers and Vector Table
Addresses........................................... 303
UART-relating Registers
UART-relating Registers .................................. 289
UPC
Clock Divider Selection Register (UPC) ............ 299
V
Vector Table
8-bit Serial I/O Interrupt Register and Vector
Table ................................................. 324
Register and Vector Table Related to 8/16-bit Capture
Timer/Counter of Interrupts ................. 184
Register and Vector Table Related to Interrupts from
Time-base Timer................................. 121
Register and Vector Table Related to the Interrupt of
the A/D Converter............................... 272
Register and Vector Table Related to the Interrupts of
an 8-bit PWM Timer ........................... 147
Register Associated with Interrupt Generation by
External Interrupt Circuit 1 and Vector
Table ................................................. 238
Register Associated with Interrupt Generation by
External Interrupt Circuit 2 and Vector
Table ................................................. 253
UART Interrupt Related Registers and Vector Table
Addresses........................................... 303
Vector Table Area
Vector Table Area
(Address: FFC0
W
Watchdog Control Register
Watchdog Control Register (WDTC) ................. 130
Watchdog Timer
Block Diagram of Watchdog Timer ................... 129
Notes on Using Watchdog Timer....................... 132
).................. 24
to FFFF
H H