Fujitsu F2MC-8L F202RA Hardware Manual page 139

Counter value
1FFFFF
H
Oscillation
stabilization
overflow
000000
H
CPU
operation start
Power-on reset (optional)
TBOF bit
TBIE bit
SLP bit
(STBC register)
STP bit
(STBC register)
Note: When the interval time selection bits of time-base timer control register (TBTC : TBC1, TBC0)
22
are set to 11 (2 /F
: Oscillation stabilization time
Figure 5.5-2 Operations of Time-base Timer
Interval cycle
(TBTC:TBC1,TBC0=11
Cleared by interrupt handling routine
Sleep
Exit stop state by IRQ7
).
CH
CHAPTER 5 TIME-BASE TIMER
Cleared by switching to stop mode
B )
Stop
Exit stop state by an external interrupt
Counter clear
(TBTC:TBR=0)
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